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Si4313-B1
3.2.3. RX State
The RX state may be entered from any of the Idle modes when the rxon bit is set to 1 in 'Register 07h. Operating
Mode and Function Control 1'. A built-in sequencer takes care of all the actions required to transition from one of
the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX
mode when going from STANDBY mode to RX mode by setting the rxon bit:
1. Enable the main digital LDO and the Analog LDOs.
2. Start up crystal oscillator and wait until ready (controlled by internal timer).
3. Enable PLL.
4. Calibrate VCO (this action is skipped when the vcocal bit is "0", default value is "1").
5. Wait until PLL settles to required receive frequency (controlled by internal timer).
6. Enable receive circuits: LNA, mixers, and ADC.
7. Calibrate ADC (RC calibration).
8. Enable receive mode in the digital modem.
Depending on the configuration of the radio all or some of the following functions will be performed automatically by
the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional)
including sync word, header check, and CRC.
3.2.4. Device Status
Add
R/W
Func/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def
02
R
Device Status
ffovfl
ffunfl
rxffem Reserved freqerr
cps[1]
cps[2]
—
The operational status of the Si4313 can be read from the Device Status register, 'Register 02h'
3.3. Interrupts
The Si4313 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown
below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers
03h-04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in
status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable
Registers (Registers 05h-06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt
status register. If the interrupt is not enabled when the event then it will not trigger the nIRQ pin, but the status may
still be read at anytime in the Interrupt Status registers.
Add R/W Func/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def
03
R
Interrupt Status 1
ifferr
Reserved
Reserved
irxffafull
iext
Reserved Reserved
Reserved
—
04
R
Interrupt Status 2
iswdet
ipreaval
ipreainval
irssi
iwut
ilbd
ichiprdy
ipor
—
05
R/W Interrupt Enable 1
enfferr
Reserved
Reserved
enrxffafull enext Reserved Reserved
Reserved
00h
06
R/W Interrupt Enable 1 enswdet enpreaval enpreainval
enrssi
enwut
enlbd
enchiprdy
enpor
01h
Rev. 1.0
21
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